Roles and Responsibilities
- Candidate would be responsible for working on physical layout development for custom IP and Testchip.
- Candidate would be responsible for development of relevant flows and methodologies for custom layout development and validation.
- Candidate will be responsible for training and ramping up junior team members
- Candidate would be responsible for taking ownership of their work and work with junior team members and guide them.
Qualification and Experience
- Bachelors or Master's Degree in Electronics/Instrumentation/Electrical Engineering or equivalent
- 6-8 years of experience in area of Custom layout design - Foundation IP, AMS.
- Relevant experience in full custom layout development and BE view generation
Essential Technical Experience
- Good understanding of Digital circuits fundamentals and SoC concepts
- Exposure to layout development in latest technologies with understanding of different layout architectures
- Experience with BE view generation and validation including layout and dependent view generation.
- Exposure to industry standard layout development/automation tools.
- Working knowledge of scripting tools (TCL, Perl, Python, Skill Programming)
- Exposure to Finfet and Fdsoi semiconductor process nodes.
Desirable Technical Experience
- Exposure and knowledge of Digital implementation flow would be an added advantage.. like synthesis, STA, P&R
Characteristics & Requirements :
- Quick learner, good problem solving and debugging skills
- Willingness to be flexible and accept new challenges
- Capable of ramping up junior team members
- Ability to work cross sites and cross teams
- Ability to engage with external customers and EDA teams
- Good analytical and reasoning skills
- Enthusiastic and self-motivated
Mentor Graphics (Sales and Services) Private LimitedExperience Level:
Mid-level ProfessionalJob Type: